Sorry your browser is not supported!

You are using an outdated browser that does not support modern web technologies, in order to use this site please update to a new browser.

Browsers supported include Chrome, FireFox, Safari, Opera, Internet Explorer 10+ or Microsoft Edge.

Geek Culture / I need to address something

Author
Message
Dark Java Dude 64
Community Leader
7
Years of Service
User Offline
Joined: 21st Sep 2010
Location: Neither here nor there nor anywhere
Posted: 7th Dec 2016 01:08 Edited at: 7th Dec 2016 01:12
And no, it's probably not what you think (regarding the moderator situation)! I need the input of other minds to figure out how best to address an interesting form of data storage...

Lately, I've been conceiving and beginning to design a very interesting project. See, for a long time, it has been a huge interest and aspiration of mine to create a fully mechanical computer working on binary (not analog!) principles. The original Z1 computer (from the 40s?) was like this, and I know that some people have built them in recent times. For the most part, though, this type of computer is nearly nonexistent. Anyway, I've modified my string logic gate design into a different sort of lever based logic gate design that effectively works on the same principle (and is still fully composable, allowing assemblies of gates without needing synchronization, which the Z1 computer actually did need). Oh, and, it should be possible to assemble the gates and other logic elements with laser cut pieces of plastic, hopefully making the overall project affordable, even if made of thousands of gates. In the mean time, I plan on doing some smaller scale prototyping with a 3D printer I ordered a week ago (still in a warehouse in China ).

Anyway, I've also come up with an interesting design for memory (I call it bead memory, as it uses the positions of small beads to store individual bits), which should be able to cram 48 kilobytes of data into a roughly 1x1.5x2 meter space (possibly smaller). To keep this design from being excessively complex, it works somewhat akin to a hard disk drive -- data is stored on a very simple medium (consisting of a small bead/ball for each bit and a specially shaped substrate) and is accessed by a far more complex "read/write head", which physically moves across the storage medium (stacked into "platters" as I call them) to access different addresses. As in an HDD, this movement of the head across the storage medium will make accessing data inherently slow. Sure, of course, the whole computer will be slow by its mechanical nature, but I expect this storage contraption to be really slow (let's arbitrarily guesstimate at least half a second per seek, much longer for seeks requiring significant head movement). Electronic computers handle this with faster and smaller RAM, which I plan to emulate with a small (probably somewhere around 512 to 1,024 bytes) bank of NAND gate memory.

Now in a real computer, at least to my understanding, this system is facilitated by a system of interrupts (processor requests data from HDD, moves onto other processing while waiting, is notified via interrupt once data from HDD is ready). To keep the processor's complexity to a minimum, I'd like to avoid implementing any sort of interrupt handling support. That said... How do you folks think I should address my storage system? I have a couple ideas myself...

First, the small memory bank could merely be representative of a of a specific address range within storage; for example, at any given time, a portion of the memory bank would be a copy of a certain address range within storage, and the two would often need to be synced back and forth. I feel like this system might work, but it wouldn't be of any benefit in situations where completely different blocks of storage are accessed alternately (due to needing to copy over an entire chunk of data each time a new block is accessed).

Another system I have in mind wouldn't provide any speed benefit; it would effectively pause the whole system clock while waiting for the storage to seek data, only to resume the clock once the data has been accessed. This would be pretty simple and would work, but all processing would be halted during storage seeks, allowing the storage to severely bottleneck the whole system.

A third system I am thinking of is related to my first system and would allow the processor to address the storage by more of a high level system of messaging. For instance, a special address within the memory bank might be dedicated to this purpose -- when the processor wants to access the storage, it would write into this special address the storage address of the data it would like to access. The storage system would see this request and would access the data at the specified address, writing the data back into a second special address in the memory bank (or vice versa, if writing data to storage). From here, the processor would be able to check for and access the data from the memory bank at its leisure, being able to continue running (on instructions stored elsewhere in the memory bank) while the storage is being accessed. I feel like this would be the best system, or maybe a hybrid of this and the first system.

Or, perhaps, I should include some sort of interrupt handling support after all? I haven't thought about how one would implement this on a subleq OISC processor, or if it would even be possible. But hey, if I can get interrupt support, I'd be on my way to support for preemptive multitasking! Running a preemptive multitasking operating system on a mechanical computer would be just the niftiest thing.

So what do you guys think? Obviously this thing is going to be incredibly slow, (maybe 5 hertz if I'm lucky?) but I'd like to keep the storage system from bottlenecking it further.

And now that I am thinking of it, the idea of implementing interrupt support is actually quite entertaining...
OUT with the ugly campaign signature and IN with some super fancy text.
Ortu
9
Years of Service
User Offline
Joined: 21st Nov 2007
Location: Austin, TX
Posted: 7th Dec 2016 06:02
Quote: " I need to address something"


I see what you did there

cool to see this project progressing so far. Video or it didn't happen!

Option 3 seems reasonable, interrupt support is a good goal.

This project seems built for multi-threading


A single player RPG featuring a branching, player driven storyline of meaningful choices and multiple endings alongside challenging active combat and intelligent AI.
http://games.joshkirklin.com/sulium
Dark Java Dude 64
Community Leader
7
Years of Service
User Offline
Joined: 21st Sep 2010
Location: Neither here nor there nor anywhere
Posted: 7th Dec 2016 06:33 Edited at: 7th Dec 2016 06:35
Quote: "I see what you did there"
Tehe!

Quote: "cool to see this project progressing so far. Video or it didn't happen!"
Haha, it's mostly just in my mind and on drawings on paper so far. But I hope to get some 3D models whipped up before long, and hopefully once my printer ships, I will be able to start building some prototypes.

Quote: "interrupt support is a good goal."
Yeah, the more I think about it, the more I want it. I am planning on using a subleq OISC architecture, so I am not sure how exactly that all would work. I suppose I could designate one of the addresses in the memory bank to hold a jump address for interrupt handling, then hardwire the processor to automatically jump to that address when it receives an interrupt.

Quote: "This project seems built for multi-threading"


Logisim is a really neat logic circuit simulator, so I should be able to use that to prototype the logical design of the whole system before I even build anything. Nifty!
OUT with the ugly campaign signature and IN with some super fancy text.

Login to post a reply

Server time is: 2017-11-20 13:09:54
Your offset time is: 2017-11-20 13:09:54